#ifndef	S5PV210_H
#define	S5PV210_H

#include <arch/type.h>

#define	MEM(addr)	*(volatile unsigned long *)(addr)

#define	GPA0CON						*(volatile unsigned long *)0xE0200000

// Memory controller
typedef struct {
	xt_u32_t	BWSCON;
	xt_u32_t	BANKCON[8];
	xt_u32_t	REFRESH;
	xt_u32_t	BANKSIZE;
	xt_u32_t	MRSRB6;
	xt_u32_t	MRSRB7;
}S5PV210_MEMCTL;


// USB HOST
typedef struct {
	xt_u32_t	HcRevision;
	xt_u32_t	HcControl;
	xt_u32_t	HcCommonStatus;
	xt_u32_t	HcInterruptStatus;
	xt_u32_t	HcInterruptEnable;
	xt_u32_t	HcInterruptDisable;
	xt_u32_t	HcHCCA;
	xt_u32_t	HcPeriodCuttendED;
	xt_u32_t	HcControlHeadED;
	xt_u32_t	HcControlCurrentED;
	xt_u32_t	HcBulkHeadED;
	xt_u32_t	HcBuldCurrentED;
	xt_u32_t	HcDoneHead;
	xt_u32_t	HcRmInterval;
	xt_u32_t	HcFmRemaining;
	xt_u32_t	HcFmNumber;
	xt_u32_t	HcPeriodicStart;
	xt_u32_t	HcLSThreshold;
	xt_u32_t	HcRhDescriptorA;
	xt_u32_t	HcRhDescriptorB;
	xt_u32_t	HcRhStatus;
	xt_u32_t	HcRhPortStatus1;
	xt_u32_t	HcRhPortStatus2;
}S5PV210_USB_HOST;


// INTERRUPT
typedef struct {
	xt_u32_t	SRCPND;
	xt_u32_t	INTMOD;
	xt_u32_t	INTMSK;
	xt_u32_t	PRIORITY;
	xt_u32_t	INTPND;
	xt_u32_t	INTOFFSET;
}S5PV210_INTERRUPT;


// DMAS
typedef struct {
	xt_u32_t	DISRC;
	xt_u32_t	DIDST;
	xt_u32_t	DCON;
	xt_u32_t	DSTAT;
	xt_u32_t	DCSRC;
	xt_u32_t	DCDST;
	xt_u32_t	DMASKTRIG;
}S5PV210_DMA;

// CLOCK & POWER MANAGEMENT
typedef struct {
	xt_u32_t	LOCKTIME;
	xt_u32_t	MPLLCON;
	xt_u32_t	UPLLCON;
	xt_u32_t	CLKCON;
	xt_u32_t	CLKSLOW;
	xt_u32_t	CLKDIVN;
}S5PV210_CLOCK_POWER;


// LCD CONTROLLER
typedef struct {
	xt_u32_t	LCDCON1;
	xt_u32_t	LCDCON2;
	xt_u32_t	LCDCON3;
	xt_u32_t	LCDCON4;
	xt_u32_t	LCDCON5;
	xt_u32_t	LCDSADDR1;
	xt_u32_t	LCDSADDR2;
	xt_u32_t	LCDSADDR3;
	xt_u32_t	REDLUT;
	xt_u32_t	GREENLUT;
	xt_u32_t	BLUELUT;
	xt_u32_t	res[8];
	xt_u32_t	DITHMODE;
	xt_u32_t	TPAL;
}S5PV210_LCD;


// NAND FLASH
typedef struct {
	xt_u32_t	NFCONF;
	xt_u32_t	NFCMD;
	xt_u32_t	NFADDR;
	xt_u32_t	NFDATA;
	xt_u32_t	NFSTAT;
	xt_u32_t	NFECC;
}S3C2410_NAND;


// UART
typedef struct {
	xt_u32_t	ULCON;
	xt_u32_t	UCON;
	xt_u32_t	UFCON;
	xt_u32_t	UMCON;
	xt_u32_t	UTRSTAT;
	xt_u32_t	UERSTAT;
	xt_u32_t	UFSTAT;
	xt_u32_t	UMSTAT;
	xt_u8_t		UTXH;
	xt_u8_t		res1[3];
	xt_u8_t		URXH;
	xt_u8_t		res2[3];
	xt_u32_t	UBRDIV;
}S5PV210_UART;

#define s5pv210_uart0			((volatile S5PV210_UART *)0XE2900000)
#define s5pv210_uart1			((volatile S5PV210_UART *)0XE2900400)
#define s5pv210_uart2			((volatile S5PV210_UART *)0XE2900800)
#define s5pv210_uart3			((volatile S5PV210_UART *)0XE2900C00)

// PWM TIMER
typedef struct {
	xt_u32_t	TCNTB;
	xt_u32_t	TCMPB;
	xt_u32_t	TCNTO;
}S5PV210_TIMER;

typedef struct {
	xt_u32_t	TCFG0;
	xt_u32_t	TCFG1;
	xt_u32_t	TCON;
	S5PV210_TIMER	ch[4];
	xt_u32_t	TCNTB4;
	xt_u32_t	TCNTO4;
}S5PV210_TIMERS;

// USB DEVICE
typedef struct {
	xt_u8_t	EP_FIFO_REG;
	xt_u8_t	res[3];
}S5PV210_USB_DEV_FIFOS;

typedef struct {
	xt_u8_t	EP_DMA_CON;
	xt_u8_t	res1[3];
	xt_u8_t	EP_DMA_UNIT;
	xt_u8_t	res2[3];
	xt_u8_t	EP_DMA_FIFO;
	xt_u8_t	res3[3];
	xt_u8_t	EP_DMA_TTC_L;
	xt_u8_t	res4[3];
	xt_u8_t	EP_DMA_TTC_M;
	xt_u8_t	res5[3];
	xt_u8_t	EP_DMA_TTC_H;
	xt_u8_t	res6[3];
}S5PV210_USB_DEV_DMAS;

typedef struct {
	xt_u8_t	FUNC_ADDR_REG;
	xt_u8_t	res1[3];
	xt_u8_t	PWR_REG;
	xt_u8_t	res2[3];
	xt_u8_t	EP_INT_REG;
	xt_u8_t	res3[15];
	xt_u8_t	USB_INT_REG;
	xt_u8_t	res4[3];
	xt_u8_t	EP_INT_EN_REG;
	xt_u8_t	res5[15];
	xt_u8_t	USB_INT_EN_REG;
	xt_u8_t	res6[3];
	xt_u8_t	FRAME_NUM1_REG;
	xt_u8_t	res7[3];
	xt_u8_t	FRAME_NUM2_REG;
	xt_u8_t	res8[3];
	xt_u8_t	INDEX_REG;
	xt_u8_t	res9[7];
	xt_u8_t	MAXP_REG;
	xt_u8_t	res10[7];
	xt_u8_t	EP0_CSR_IN_CSR1_REG;
	xt_u8_t	res11[3];
	xt_u8_t	IN_CSR2_REG;
	xt_u8_t	res12[3];
	xt_u8_t	OUT_CSR1_REG;
	xt_u8_t	res13[7];
	xt_u8_t	OUT_CSR2_REG;
	xt_u8_t	res14[3];
	xt_u8_t	OUT_FIFO_CNT1_REG;
	xt_u8_t	res15[3];
	xt_u8_t	OUT_FIFO_CNT2_REG;
	xt_u8_t	res16[3];
	S5PV210_USB_DEV_FIFOS	fifo[5];
	S5PV210_USB_DEV_DMAS	dma[5];
}S5PV210_USB_DEVICE;


// WATCH DOG TIMER
typedef struct {
	xt_u32_t	WTCON;
	xt_u32_t	WTDAT;
	xt_u32_t	WTCNT;
}S5PV210_WATCHDOG;


// IIC
typedef struct {
	xt_u32_t	IICCON;
	xt_u32_t	IICSTAT;
	xt_u32_t	IICADD;
	xt_u32_t	IICDS;
}S5PV210_I2C;


// IIS
typedef struct {
	xt_u16_t	IISCON;
	xt_u16_t	res1;
	xt_u16_t	IISMOD;
	xt_u16_t	res2;
	xt_u16_t	IISPSR;
	xt_u16_t	res3;
	xt_u16_t	IISFCON;
	xt_u16_t	res4;
	xt_u16_t	IISFIFO;
	xt_u16_t	res5;
}S5PV210_I2S;


// I/O PORT
typedef struct {
	xt_u16_t	IISPSR;
}S5PV210_GPIO;


// RTC
typedef struct {
	xt_u8_t	res0[64];
	xt_u8_t	RTCCON;
	xt_u8_t	res1[3];
	xt_u8_t	TICNT;
	xt_u8_t	res2[11];
	xt_u8_t	RTCALM;
	xt_u8_t	res3[3];
	xt_u8_t	ALMSEC;
	xt_u8_t	res4[3];
	xt_u8_t	ALMMIN;
	xt_u8_t	res5[3];
	xt_u8_t	ALMHOUR;
	xt_u8_t	res6[3];
	xt_u8_t	ALMDATE;
	xt_u8_t	res7[3];
	xt_u8_t	ALMMON;
	xt_u8_t	res8[3];
	xt_u8_t	ALMYEAR;
	xt_u8_t	res9[3];
	xt_u8_t	RTCRST;
	xt_u8_t	res10[3];
	xt_u8_t	BCDSEC;
	xt_u8_t	res11[3];
	xt_u8_t	BCDMIN;
	xt_u8_t	res12[3];
	xt_u8_t	BCDHOUR;
	xt_u8_t	res13[3];
	xt_u8_t	BCDDATE;
	xt_u8_t	res14[3];
	xt_u8_t	BCDDAY;
	xt_u8_t	res15[3];
	xt_u8_t	BCDMON;
	xt_u8_t	res16[3];
	xt_u8_t	BCDYEAR;
	xt_u8_t	res17[3];
}S5PV210_RTC;

// ADC
typedef struct {
	xt_u32_t	ADCCON;
	xt_u32_t	ADCDAT;
}S3C2400_ADC;

// ADC
typedef struct {
	xt_u32_t	ADCCON;
	xt_u32_t	ADCTSC;
	xt_u32_t	ADCDLY;
	xt_u32_t	ADCDAT0;
	xt_u32_t	ADCDAT1;
}S3C2410_ADC;

// SPI
typedef struct {
	xt_u32_t	SPCON;
	xt_u32_t	SPSTA;
	xt_u32_t	SPPIN;
	xt_u32_t	SPPRE;
	xt_u32_t	SPTDAT;
	xt_u32_t	SPRDAT;
	xt_u32_t	res[2];
} __attribute__((__packed__)) S5PV210_SPI_CHANNEL;


// MMC INTERFACE
typedef struct {
	xt_u8_t	MMCON;
	xt_u8_t	res1[3];
	xt_u8_t	MMCRR;
	xt_u8_t	res2[3];
	xt_u8_t	MMFCON;
	xt_u8_t	res3[3];
	xt_u8_t	MMSTA;
	xt_u8_t	res4[3];
	xt_u16_t	MMFSTA;
	xt_u16_t	res5;
	xt_u8_t	MMPRE;
	xt_u8_t	res6[3];
	xt_u16_t	MMLEN;
	xt_u16_t	res7;
	xt_u8_t	MMCR7;
	xt_u8_t	res8[3];
	xt_u32_t	MMRSP[4];
	xt_u8_t	MMCMD0;
	xt_u8_t	res9[3];
	xt_u32_t	MMCMD1;
	xt_u16_t	MMCR16;
	xt_u16_t	res10;
	xt_u8_t	MMDAT;
	xt_u8_t	res11[3];
}S3C2400_MMC;

// SD INTERFACE
typedef struct {
	xt_u32_t	SDICON;
	xt_u32_t	SDIPRE;
	xt_u32_t	SDICARG;
	xt_u32_t	SDICCON;
	xt_u32_t	SDICSTA;
	xt_u32_t	SDIRSP0;
	xt_u32_t	SDIRSP1;
	xt_u32_t	SDIRSP2;
	xt_u32_t	SDIRSP3;
	xt_u32_t	SDIDTIMER;
	xt_u32_t	SDIBSIZE;
	xt_u32_t	SDIDCON;
	xt_u32_t	SDIDCNT;
	xt_u32_t	SDIDSTA;
	xt_u32_t	SDIFSTA;
	xt_u8_t	SDIDAT;
	xt_u8_t	res[3];
	xt_u32_t	SDIIMSK;
}S3C2410_SDI;

#endif // S5PV210_H
